? semiconductor components industries, llc, 2005 june, 2005 ? rev. 13 1 publication order number: MC100EPT23/d MC100EPT23 3.3vdual differential lvpecl/lvds to lvttl translator the MC100EPT23 is a dual differential lvpecl/lvds to lvttl translator. because lvpecl (positive ecl) or lvds levels are used, only +3.3 v and ground are required. the small outline 8-lead package and the dual gate design of the ept23 makes it ideal for applications which require the translation of a clock and a data signal. the ept23 is available in only the ecl 100k standard. since there are no lvpecl outputs or an external v bb reference, the ept23 does not require both ecl standard versions. the lvpecl/lvds inputs are differential. therefore, the MC100EPT23 can accept any standard differential lvpecl/lvds input referenced from a v cc of +3.3 v. features ? 1.5 ns typical propagation delay ? maximum operating frequency > 275 mhz ? 24 ma lvttl outputs ? operating range: v cc = 3.0 v to 3.6 v with gnd = 0 v ? pb?free packages are available *for additional marking information, refer to application note and8002/d. marking diagrams* a = assembly location l = wafer lot y = year w = work week d = date code = pb?free package (note: microdot may be in either location ) ka23 alyw soic?8 d suffix case 751 1 8 tssop?8 dt suffix case 948r 1 8 1 8 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information http://onsemi.com kpt23 alyw 1 8 dfn8 mn suffix case 506aa 3t m 14
MC100EPT23 http://onsemi.com 2 1 2 3 45 6 7 8 q0 gnd v cc figure 1. 8?lead pinout and logic diagram d0 q1 d1 d1 d0 lvpecl lvttl (top view) table 1. pin description pin function q0, q1 lvttl outputs d0**, d1** d0 **, d1 ** differential lvpecl inputs v cc positive supply gnd ground ** pins will default to v cc /2 when left open. table 2. attributes characteristics value internal input pulldown resistor 50 k internal input pullup resistor 50 k esd protection human body model machine model charged device model > 1500 v > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 91 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc power supply gnd = 0 v 3.8 v v i input voltage gnd = 0 v v i v cc 3.8 v i out output current continuous surge 50 100 ma ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm soic?8 soic?8 190 130 c/w c/w jc thermal resistance (junction?to?case) standard board soic?8 41 to 44 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm tssop?8 tssop?8 185 140 c/w c/w jc thermal resistance (junction?to?case) standard board tssop?8 41 to 44 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm dfn8 dfn8 129 84 c/w c/w t sol wave solder pb pb?free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected.
MC100EPT23 http://onsemi.com 3 table 4. pecl dc characteristics v cc = 3.3 v, gnd = 0 v (note 2) symbol characteristic ?40 c 25 c 85 c unit min typ max min typ max min typ max i cch power supply current (outputs set to high) 10 18 25 10 18 25 10 18 25 ma i ccl power supply current (outputs set to low) 15 26 36 15 26 36 15 26 36 ma v ih input high voltage 2075 2420 2075 2420 2075 2420 mv v il input low voltage 1355 1675 1355 1675 1355 1675 mv v ihcmr input high voltage common mode range (note 3) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current d d ?150 ?150 ?150 ?150 ?150 ?150 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. all values vary 1:1 with v cc . 3. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 5. ttl dc characteristics v cc = 3.3 v, gnd = 0.0 v, t a = ?40 c to 85 c symbol characteristic condition min typ max unit v oh output high voltage i oh = ?3.0 ma 2.4 v v ol output low voltage i ol = 24 ma 0.5 v i os output short circuit current ?180 ?50 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. table 6. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0.0 v (note 4) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max f max maximum frequency (figure 2) 275 350 275 350 275 350 mhz t plh , t phl propagation delay to output differential (note 5) 1.2 1.2 1.5 1.5 1.8 1.8 1.2 1.1 1.5 1.5 1.8 1.8 1.3 1.1 1.7 1.5 2.4 1.8 ns t sk+ + t sk? ? t skpp output?to?output skew++ output?to?output skew?? part?to?part skew (note 6) 15 35 70 60 80 500 15 40 70 70 80 500 30 40 140 125 80 500 ps t jitter random clock jitter (rms) (figure 2) 5 10 5 10 5 10 ps v pp input voltage swing (differential configuration) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times (0.8 v ? 2.0 v) q, q 330 600 900 330 600 900 330 650 900 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measured with a 750 mv 50% duty?cycle clock source. r l = 500 to gnd and c l = 20 pf to gnd. refer to figure 3. 5. reference (v cc = 3.3v 5%; gnd = 0 v) 6. skews are measured between outputs under identical conditions.
MC100EPT23 http://onsemi.com 4 figure 2. typical v oh / jitter versus frequency (25 c) frequency (mhz) v oh (v) 0.0 1.0 2.0 3.0 v oh v ol 0.5 v jitter random clock jitter (ps rms) 0 100 200 300 400 12 8 4 0 figure 3. ttl output loading used for device evaluation characteristic test c l *r l ac test load gnd *c l includes fixture capacitance application ttl receiver
MC100EPT23 http://onsemi.com 5 ordering information device package shipping ? MC100EPT23d soic?8 98 units / rail MC100EPT23dg soic?8 (pb?free) 98 units / rail MC100EPT23dr2 soic?8 2500 / tape & reel MC100EPT23dr2g soic?8 (pb?free) 2500 / tape & reel MC100EPT23dt tssop?8 100 units / rail MC100EPT23dtg tssop?8 (pb?free) 100 units / rail MC100EPT23dtr2 tssop?8 2500 / tape & reel MC100EPT23dtr2g tssop?8 (pb?free) 2500 / tape & reel MC100EPT23mnr4 dfn8 1000 / tape & reel MC100EPT23mnr4g dfn8 (pb?free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1642/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
MC100EPT23 http://onsemi.com 6 package dimensions soic?8 nb case 751?07 issue af seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
MC100EPT23 http://onsemi.com 7 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 ?u? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop?8 dt suffix plastic tssop package case 948r?02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane ?w?.
MC100EPT23 http://onsemi.com 8 package dimensions dfn8 case 506aa?01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 8 x a1 seating plane e/2 e 8 x k note 3 b 8 x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k 0.20 ??? l 0.25 0.35 1 4 8 5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC100EPT23/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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